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DAC
2008
ACM
14 years 9 months ago
Federation: repurposing scalar cores for out-of-order instruction issue
Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads th...
David Tarjan, Michael Boyer, Kevin Skadron
ICIP
2000
IEEE
14 years 9 months ago
Performance Analysis of an H.263 Video Encoder for VIRAM
VIRAM (Vector Intelligent Random Access Memory) is a vector architecture processor with embedded memory, designed for portable multimedia processing devices. Its vector processing...
Thinh P. Q. Nguyen, Avideh Zakhor, Katherine A. Ye...
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
13 years 11 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
ASPDAC
2008
ACM
168views Hardware» more  ASPDAC 2008»
13 years 10 months ago
A fast two-pass HDL simulation with on-demand dump
- Simulation-based functional verification is characterized by two inherently conflicting targets: the signal visibility and simulation performance. Achieving a proper trade-off be...
Kyuho Shim, Youngrae Cho, Namdo Kim, Hyuncheol Bai...
WSC
2004
13 years 9 months ago
Implementing the High Level Architecture in the Virtual Test Bed
The Virtual Test Bed (VTB) is a prototype of a virtual engineering environment to study operations of current and future space vehicles, spaceports, and ranges. The HighLevel Arch...
José A. Sepúlveda, Luis C. Rabelo, J...