130 search results - page 20 / 26 » Architecture and Evaluation of an Asynchronous Array of Simp... |
EUROSYS
2010
ACM
14 years 5 months ago
2010
ACM
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
VEE
2010
ACM
14 years 3 months ago
2010
ACM
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
In many scientific applications, significant time is spent tuning codes for a particular highperformance architecture. Tuning approaches range from the relatively nonintrusive (...
ACMMSP
2004
ACM
14 years 1 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...