Sciweavers

592 search results - page 95 / 119
» Architecture and Implementation of an Embedded Wormhole
Sort
View
MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
14 years 2 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
CASES
2006
ACM
14 years 2 months ago
High-level languages for small devices: a case study
In this paper we study, through a concrete case, the feasibility of using a high-level, general-purpose logic language in the design and implementation of applications targeting w...
Manuel Carro, José F. Morales, Henk L. Mull...
ISPASS
2005
IEEE
14 years 2 months ago
Analysis of Network Processing Workloads
Abstract— Network processing is becoming an increasingly important paradigm as the Internet moves towards an architecture with more complex functionality inside the network. Mode...
Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf
MM
2005
ACM
167views Multimedia» more  MM 2005»
14 years 2 months ago
SensEye: a multi-tier camera sensor network
This paper argues that a camera sensor network containing heterogeneous elements provides numerous benefits over traditional homogeneous sensor networks. We present the design an...
Purushottam Kulkarni, Deepak Ganesan, Prashant J. ...
SAMOS
2005
Springer
14 years 1 months ago
Sandbridge Software Tools
—We describe the generation of the simulation environment for the Sandbridge Sandblaster multithreaded processor. The processor model is described using the Sandblaster architect...
C. John Glossner, Sean Dorward, Sanjay Jinturkar, ...