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MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
14 years 1 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
SIGCOMM
2010
ACM
13 years 6 months ago
SourceSync: a distributed wireless architecture for exploiting sender diversity
Diversity is an intrinsic property of wireless networks. Recent years have witnessed the emergence of many distributed protocols like ExOR, MORE, SOAR, SOFT, and MIXIT that exploi...
Hariharan Rahul, Haitham Hassanieh, Dina Katabi
SIGCOMM
2006
ACM
14 years 19 days ago
XORs in the air: practical wireless network coding
— This paper proposes COPE, a new architecture for wireless mesh networks. In addition to forwarding packets, routers mix (i.e., code) packets from different sources to increase ...
Sachin Katti, Hariharan Rahul, Wenjun Hu, Dina Kat...
HPCA
2009
IEEE
14 years 7 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
TOMACS
1998
140views more  TOMACS 1998»
13 years 6 months ago
Technical Note: A Hierarchical Computer Architecture Design and Simulation Environment
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
Paul S. Coe, Fred W. Howell, Roland N. Ibbett, Lau...