6 search results - page 1 / 2 » Architecture design of an H.264 AVC decoder for real-time FP... |
ASAP
2006
IEEE
13 years 9 months ago
2006
IEEE
This paper discusses hardware development of a realtime H.264/AVC video decoder. Synthesis results are presented for example implementations of the inverse quantization, inverse t...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- This paper presents an H.264/AVC baseline profile decoder based on a SoC platform design methodology. The overall decoding throughput is increased by optimized software and a ded...
ICMCS
2006
IEEE
14 years 1 months ago
2006
IEEE
— A major challenge in the design of any real time system is the proper selection of implementation and platform alternatives. In this paper, a suitable FPGA-based design of the ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The ha...