Architecture design of an H.264/AVC decoder for real-time FPGA implementation

This paper discusses hardware development of a realtime H.264/AVC video decoder. Synthesis results are presented for example implementations of the inverse quantization, inverse transform, and deblocking filter stages. A hardware architecture is also proposed for FPGA implementations of a complete video decoder.

• Type: Conference
• Year: 2006
• Where: ASAP
• Authors: Thomas Warsaw, Marcin Lukowiak
• Keywords: ASAP 2006, Complete Video Decoder, H.264/AVC Video Decoder, Hardware, Video Decoder