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RTSS
1999
IEEE
14 years 1 months ago
Timing Anomalies in Dynamically Scheduled Microprocessors
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
Thomas Lundqvist, Per Stenström
TJS
2008
95views more  TJS 2008»
13 years 8 months ago
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Akshat Verma, Sandeep Sen
CORR
2008
Springer
187views Education» more  CORR 2008»
13 years 9 months ago
Securing U-Healthcare Sensor Networks using Public Key Based Scheme
Recent emergence of electronic culture uplifts healthcare facilities to a new era with the aid of wireless sensor network (WSN) technology. Due to the sensitiveness of medical data...
Md. Mokammel Haque, Al-Sakib Khan Pathan, Choong S...
MICRO
2009
IEEE
507views Hardware» more  MICRO 2009»
14 years 3 months ago
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efficient manner. However, PCM cells can endure on...
Moinuddin K. Qureshi, John Karidis, Michele France...
CIG
2005
IEEE
14 years 2 months ago
Forcing Neurocontrollers to Exploit Sensory Symmetry Through Hard-wired Modularity in the Game of Cellz
Several attempts have been made in the past to construct encoding schemes that allow modularity to emerge in evolving systems, but success is limited. We believe that in order to c...
Julian Togelius, Simon M. Lucas