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SIPS
2006
IEEE
14 years 1 months ago
Architecture-Aware LDPC Code Design for Software Defined Radio
Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of the...
Yuming Zhu, Chaitali Chakrabarti
ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
14 years 4 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
13 years 11 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng
UML
2004
Springer
14 years 25 days ago
SoftContract: Model-Based Design of Error-Checking Code and Property Monitors
This paper discusses a model-based design flow for requirements in distributed embedded software development. Such requirements are specified using a language similar to Linear T...
Luciano Lavagno, Marco Di Natale, Alberto Ferrari,...
CORR
2008
Springer
106views Education» more  CORR 2008»
13 years 7 months ago
Construction of Near-Optimum Burst Erasure Correcting Low-Density Parity-Check Codes
In this paper, a simple and effective tool for the design of low-density parity-check (LDPC) codes for iterative correction of bursts of erasures is presented. The design method co...
Enrico Paolini, Marco Chiani