ICCAD 2002 - PDF Preprint Papers

ICCAD 2002 International Conference on Computer-Aided Design

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ICCAD
2002
IEEE

227views Hardware» more ICCAD 2002»

Generic ILP versus specialized 0-1 ILP: an update

14 years 8 months ago

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Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further use...

Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...

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Id	Views	Title	Status

1	227	Generic ILP versus specialized 0-1 ILP: an update	claim
2	189	Reversible logic circuit synthesis	claim
3	176	High capacity and automatic functional extraction tool for industrial VLSI circuit designs	claim
4	175	Efficient model order reduction via multi-node moment matching	claim
5	163	Sub-90nm technologies: challenges and opportunities for CAD	claim
6	161	Non-tree routing for reliability and yield improvement	claim
7	160	Folding of logic functions and its application to look up table compaction	claim
8	157	Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads	claim
9	154	Concurrent flip-flop and repeater insertion for high performance integrated circuits	claim
10	152	Efficient instruction encoding for automatic instruction set design of configurable ASIPs	claim
11	149	Battery-aware power management based on Markovian decision processes	claim
12	149	Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step	claim
13	146	Test-model based hierarchical DFT synthesis	claim
14	146	Conflict driven learning in a quantified Boolean Satisfiability solver	claim
15	145	A local circuit topology for inductive parasitics	claim
16	144	Subthreshold leakage modeling and reduction techniques	claim
17	143	A Markov chain sequence generator for power macromodeling	claim
18	142	SAT and ATPG: Boolean engines for formal hardware verification	claim
19	141	A hierarchical modeling framework for on-chip communication architectures	claim
20	129	Transmission line design of clock trees	claim
21	127	Leakage power modeling and reduction with data retention	claim
22	126	Robust and passive model order reduction for circuits containing susceptance elements	claim
23	125	Circuit power estimation using pattern recognition techniques	claim
24	124	Comprehensive frequency-dependent substrate noise analysis using boundary element methods	claim
25	124	Interface specification for reconfigurable components	claim
26	124	Symbolic pointer analysis	claim
27	122	Schedulability analysis of multiprocessor real-time applications with stochastic task execution times	claim
28	120	CAD computation for manufacturability: can we save VLSI technology from itself?	claim
29	117	An enhanced multilevel routing system	claim
30	117	An energy-conscious algorithm for memory port allocation	claim
31	116	Conflict driven techniques for improving deterministic test pattern generation	claim
32	113	INDUCTWISE: inductance-wise interconnect simulator and extractor	claim
33	113	Interconnect-aware high-level synthesis for low power	claim
34	112	ATPG-based logic synthesis: an overview	claim
35	110	Whirlpool PLAs: a regular logic structure and their synthesis	claim
36	110	Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects	claim
37	109	Methods for true power minimization	claim
38	108	SiSMA: a statistical simulator for mismatch analysis of MOS ICs	claim
39	108	A precorrected-FFT method for simulating on-chip inductance	claim
40	108	Implicit treatment of substrate and power-ground losses in return-limited inductance extraction	claim
41	107	Characteristic faults and spectral information for logic BIST	claim
42	107	Theoretical and practical validation of combined BEM/FEM substrate resistance modeling	claim
43	106	Throughput-driven IC communication fabric synthesis	claim
44	104	A new enhanced SPFD rewiring algorithm	claim
45	103	Synthesis of customized loop caches for core-based embedded systems	claim
46	103	A realistic variable voltage scheduling model for real-time applications	claim
47	103	A novel scan architecture for power-efficient, rapid test	claim
48	103	A technology-independent CAD tool for ESD protection device extraction: ESDExtractor	claim
49	101	Frame-based dynamic voltage and frequency scaling for a MPEG decoder	claim
50	101	FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materials	claim
51	100	Multi-objective circuit partitioning for cutsize and path-based delay minimization	claim
52	100	On theoretical and practical considerations of path selection for delay fault testing	claim
53	100	Optimal buffered routing path constructions for single and multiple clock domain systems	claim
54	98	Topologically constrained logic synthesis	claim
55	98	On-chip interconnect modeling by wire duplication	claim
56	98	Efficient mixed-domain analysis of electrostatic MEMS	claim
57	94	High-level synthesis of distributed logic-memory architectures	claim
58	93	Refining switching window by time slots for crosstalk noise calculation	claim
59	92	Optimization of a fully integrated low power CMOS GPS receiver	claim
60	92	ECO algorithms for removing overlaps between power rails and signal wires	claim
61	90	Molecular electronics: devices, systems and tools for gigagate, gigabit chips	claim
62	89	Free space management for cut-based placement	claim
63	87	Schematic-based lumped parameterized behavioral modeling for suspended MEMS	claim
64	87	A novel framework for multilevel routing considering routability and performance	claim
65	86	Extraction and LVS for mixed-domain integrated MEMS layouts	claim
66	85	On undetectable faults in partial scan circuits	claim
67	83	Track assignment: a desirable intermediate step between global routing and detailed routing	claim
68	82	Simplification of non-deterministic multi-valued networks	claim
69	82	Hardware/software partitioning of software binaries	claim
70	81	Making Fourier-envelope simulation robust	claim
71	80	Minimizing power across multiple technology and design levels	claim
72	79	Analysis and optimization of substrate noise coupling in single-chip RF transceiver design	claim
73	76	WTA: waveform-based timing analysis for deep submicron circuits	claim
74	74	The A to Z of SoCs	claim
75	73	Shaping interconnect for uniform current density	claim
76	71	Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms	claim
77	71	Timing-driven placement using design hierarchy guided constraint generation	claim
78	70	Fast methods for simulation of biomolecule electrostatics	claim

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