125 search results - page 24 / 25 » Area and delay trade-offs in the circuit and architecture de... |
TVLSI
2008
13 years 6 months ago
2008
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...