125 search results - page 6 / 25 » Area and delay trade-offs in the circuit and architecture de... |
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
TCAD
2010
13 years 2 months ago
2010
In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the sa...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
FPGA
2001
ACM
13 years 12 months ago
2001
ACM
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...