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» Area-efficient error protection for caches
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DSN
2003
IEEE
14 years 22 days ago
ICR: In-Cache Replication for Enhancing Data Cache Reliability
Processor caches already play a critical role in the performance of today’s computer systems. At the same time, the data integrity of words coming out of the caches can have ser...
Wei Zhang 0002, Sudhanva Gurumurthi, Mahmut T. Kan...
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 1 months ago
Low-cost protection for SER upsets and silicon defects
Extreme transistor scaling trends in silicon technology are soon to reach a point where manufactured systems will suffer from limited device reliability and severely reduced life...
Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kyp...
PRDC
2005
IEEE
14 years 1 months ago
Partitioned Cache Shadowing for Deep Sub-Micron (DSM) Regime
An important issue in modern cache designs is bridging the gap between wire and device delays. This warrants the use of more regular and modular structures to mask wire latencies....
Heng Xu, Arun K. Somani
VLDB
1997
ACM
104views Database» more  VLDB 1997»
13 years 11 months ago
Integrating Reliable Memory in Databases
Abstract. Recent results in the Rio project at the University of Michigan show that it is possible to create an area of main memory that is as safe as disk from operating system cr...
Wee Teck Ng, Peter M. Chen
DSN
2005
IEEE
14 years 1 months ago
ReStore: Symptom Based Soft Error Detection in Microprocessors
Device scaling and large scale integration have led to growing concerns about soft errors in microprocessors. To date, in all but the most demanding applications, implementing par...
Nicholas J. Wang, Sanjay J. Patel