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MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
13 years 11 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
FPL
2006
Springer
96views Hardware» more  FPL 2006»
13 years 11 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling
GECCO
2000
Springer
182views Optimization» more  GECCO 2000»
13 years 11 months ago
A Novel Evolvable Hardware Framework for the Evolution of High Performance Digital Circuits
This paper presents a novel evolvable hardware framework for the automated design of digital circuits for high performance applications. The technique evolves circuits correspondi...
Ben I. Hounsell, Tughrul Arslan
VMV
2004
183views Visualization» more  VMV 2004»
13 years 8 months ago
CGiS, a new Language for Data-parallel GPU Programming
In the last few years, GPUs have become new, promising targets for general purpose programming. Their inherent parallel architecture makes them particularly suited for scientific ...
Nicolas Fritz, Philipp Lucas, Philipp Slusallek
ADHOC
2010
163views more  ADHOC 2010»
13 years 7 months ago
A probabilistic method for cooperative hierarchical aggregation of data in VANETs
We propose an algorithm for the hierarchical aggregation of observations in dissemination-based, distributed traffic information systems. Instead of transmitting observed paramete...
Christian Lochert, Björn Scheuermann, Martin ...