184 search results - page 34 / 37 » Arity Raiser and its Use in Program Specialization |
ISCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
CANPC
1999
Springer
13 years 11 months ago
1999
Springer
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
ISCA
2002
IEEE
13 years 6 months ago
2002
IEEE
In this paper, we consider the tree task graphs which arise from many important programming paradigms such as divide and conquer, branch and bound etc., and the linear task-graphs...
PC
2007
13 years 6 months ago
2007
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
HIPEAC
2011
Springer
12 years 6 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...