67 search results - page 7 / 14 » Array-of-arrays architecture for parallel floating point mul... |
MICRO
1998
IEEE
14 years 2 months ago
1998
IEEE
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
COMSWARE
2007
IEEE
14 years 4 months ago
2007
IEEE
The Elliptic Curve Digital Signature Algorithm admits a natural parallelization wherein the point multiplication step can be split in two parts and executed in parallel. Further pa...
TPDS
2008
13 years 10 months ago
2008
: The STI CELL processor introduces pioneering solutions in processor architecture. At the same time it presents new challenges for the development of numerical algorithms. One is ...
SIGMETRICS
2008
ACM
13 years 10 months ago
2008
ACM
Per-flow network measurement at Internet backbone links requires the efficient maintanence of large arrays of statistics counters at very high speeds (e.g. 40 Gb/s). The prevailin...
EUROPAR
2009
Springer
14 years 2 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...