Sciweavers

4287 search results - page 786 / 858
» Assessing Architectural Complexity
Sort
View
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
14 years 4 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
14 years 4 months ago
Finding concurrency bugs with context-aware communication graphs
Incorrect thread synchronization often leads to concurrency bugs that manifest nondeterministically and are difficult to detect and fix. Past work on detecting concurrency bugs ...
Brandon Lucia, Luis Ceze
CF
2009
ACM
14 years 4 months ago
A light-weight fairness mechanism for chip multiprocessor memory systems
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
Magnus Jahre, Lasse Natvig
ICPP
2008
IEEE
14 years 4 months ago
Optimizing JPEG2000 Still Image Encoding on the Cell Broadband Engine
JPEG2000 is the latest still image coding standard from the JPEG committee, which adopts new algorithms such as Embedded Block Coding with Optimized Truncation (EBCOT) and Discret...
Seunghwa Kang, David A. Bader
ICDE
2007
IEEE
107views Database» more  ICDE 2007»
14 years 4 months ago
An Integrated Platform for Spatial Data Mining within a GIS Environment
The strength of GIS is in providing a rich data infrastructure for combining disparate data in meaningful ways by using a spatial arrangement (e.g., proximity). As a toolbox, a GI...
Annalisa Appice, Antonietta Lanza, Donato Malerba