Abstract. In this paper we describe an Integrated Development System for Instructional Model for E-learning (INDESIME) to create and to maintain instructional models using adaptive...
The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
In this paper we present the results of a study designed to evaluate the computer-based methods of learning American Sign Language (ASL). We describe a method including an initial...
Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such ...