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» Assessing Instructional Technology
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IEEEPACT
2008
IEEE
14 years 2 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...
IMC
2006
ACM
14 years 1 months ago
Semi-automated discovery of application session structure
While the problem of analyzing network traffic at the granularity of individual connections has seen considerable previous work and tool development, understanding traffic at a ...
Jayanthkumar Kannan, Jaeyeon Jung, Vern Paxson, Ca...
CGO
2005
IEEE
14 years 1 months ago
Optimizing Sorting with Genetic Algorithms
The growing complexity of modern processors has made the generation of highly efficient code increasingly difficult. Manual code generation is very time consuming, but it is oft...
Xiaoming Li, María Jesús Garzar&aacu...
ICALT
2005
IEEE
14 years 1 months ago
ActiveTutor
In this paper we present an architecture dedicated to an intelligently assisted educational tool which integrates within a unified framework software rational agents both at the m...
Jean Pierre Fournier
RTAS
2005
IEEE
14 years 1 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...