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134
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DATE
2009
IEEE
138views Hardware» more  DATE 2009»
15 years 10 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
CCGRID
2005
IEEE
15 years 9 months ago
Application-level simulation modelling of large grids
The simulation of large grids requires the generation of grid instances and an approximation of grid components’ behaviour. To generate grid instances, this paper outlines a set...
Serafeim Zanikolas, Rizos Sakellariou
124
Voted
CLUSTER
2008
IEEE
15 years 10 months ago
Divisible load scheduling with improved asymptotic optimality
—Divisible load model allows scheduling algorithms that give nearly optimal makespan with practical computational complexity. Beaumont et al. have shown that their algorithm prod...
Reiji Suda
121
Voted
ICPPW
2003
IEEE
15 years 9 months ago
Load Balancing on PC Clusters with the Super-Programming Model
Recent work in high-performance computing has shifted attention to PC clusters.. For PC-clusters, member nodes are independent computers connected by generalpurpose networks. The ...
Dejiang Jin, Sotirios G. Ziavras
HPCA
1999
IEEE
15 years 8 months ago
A Study of Control Independence in Superscalar Processors
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under p...
Eric Rotenberg, Quinn Jacobson, James E. Smith