We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solv...
Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N...
Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...
Wei-Shen Wang, Vladik Kreinovich, Michael Orshansk...
Automated cell placement is a critical problem in VLSI physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently rec...
Abstract. Context-sensitive analysis provides information which is potentially more accurate than that provided by context-free analysis. Such information can then be applied in or...