119 search results - page 19 / 24 » Automated Modeling of Custom Digital Circuits for Test |
ICSE
2007
IEEE-ACM
14 years 8 months ago
2007
IEEE-ACM
Designing complex multi-tier applications that must meet strict performance requirements is a challenging software engineering problem. Ideally, the application architect could de...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
The number and magnitude of process variation sources are increasing as we scale further into the nano regime. Today's most successful response surface methods limit us to lo...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
FPGA
2003
ACM
14 years 1 months ago
2003
ACM
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
IEICET
2008
13 years 8 months ago
2008
This paper studies impact of the well edge proximity effect on digital circuit delay, based on model parameters extracted from test structures in an industrial 65nm wafer process. ...