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2009
ACM
14 years 4 months ago
Router designs for elastic buffer on-chip networks
This paper explores the design space of elastic buffer (EB) routers by evaluating three representative designs. We propose an enhanced two-stage EB router which maximizes through...
George Michelogiannakis, William J. Dally
IJFCS
1998
67views more  IJFCS 1998»
13 years 9 months ago
Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits
Directed acyclic graphs (dags) are often used to model circuits. Path lengths in such dags represent circuit delays. In the vertex splitting problem, the objective is to determine...
Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni
CHARME
2001
Springer
98views Hardware» more  CHARME 2001»
14 years 1 months ago
Hardware Synthesis Using SAFL and Application to Processor Design
Abstract. We survey the work done so far in the FLaSH project (Functional Languages for Synthesising Hardware) in which the core ideas are (i) using a functional language SAFL to d...
Alan Mycroft, Richard Sharp
IPPS
1998
IEEE
14 years 1 months ago
Design and Implementation of a Parallel I/O Runtime System for Irregular Applications
In this paper we present the design, implementation and evaluation of a runtime system based on collective I/O techniques for irregular applications. We present two models, namely...
Jaechun No, Sung-Soon Park, Jesús Carretero...
TVLSI
2008
151views more  TVLSI 2008»
13 years 9 months ago
Guest Editorial Special Section on Design Verification and Validation
ion levels. The framework also supports the generation of test constraints, which can be satisfied using a constraint solver to generate tests. A compositional verification approac...
I. Harris, D. Pradhan