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Automated Pipeline Design
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FAR-DS: Full-Plane AWE Routing with Driver Sizing
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Jiang Hu, Sachin S. Sapatnekar
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Enhancing Simulation with BDDs and ATPG
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Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann
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Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction
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computing.ece.vt.edu
Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
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A Methodology for Accurate Performance Evaluation in Architecture Exploration
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George Hadjiyiannis, Pietro Russo, Srinivas Devada...
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A Model for Scheduling Protocol-Constrained Components and Environments
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Steve Haynal, Forrest Brewer
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