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DAC 1999 Design Automation Conference

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DAC
1999
ACM

278views Computer Architecture» more DAC 1999»

Hardware Compilation for FPGA-Based Configurable Computing Machines

14 years 3 months ago

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Xiaohan Zhu, Bill Lin

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Id	Views	Title	Status

1	278	Hardware Compilation for FPGA-Based Configurable Computing Machines	claim
2	224	Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration	claim
3	205	Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits	claim
4	201	LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures	claim
5	185	A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs	claim
6	182	A Study in Coverage-Driven Test Generation	claim
7	179	A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design	claim
8	179	Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications	claim
9	172	Buffer Insertion with Accurate Gate and Interconnect Delay Computation	claim
10	169	Performance-Driven Scheduling with Bit-Level Chaining	claim
11	168	Memory Exploration for Low Power, Embedded Systems	claim
12	167	Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits	claim
13	167	On ILP Formulations for Built-In Self-Testable Data Path Synthesis	claim
14	166	An Efficient Lyapunov Equation-Based Approach for Generating Reduced-Order Models of Interconnect	claim
15	165	Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor	claim
16	164	Interconnect Analysis: From 3-D Structures to Circuit Models	claim
17	159	Cycle-Accurate Simulation of Energy Consumption in Embedded Systems	claim
18	158	On-Chip Inductance Issues in Multiconductor Systems	claim
19	157	Power Efficient Mediaprocessors: Design Space Exploration	claim
20	155	Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices	claim
21	155	Multilevel k-way Hypergraph Partitioning	claim
22	154	A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems	claim
23	150	Constraint Driven Code Selection for Fixed-Point DSPs	claim
24	150	System-Level Hardware/Software Trade-offs	claim
25	149	Micro Architecture Coverage Directed Generation of Test Programs	claim
26	149	Vex - A CAD Toolbox	claim
27	149	Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages	claim
28	148	ipChinook: an Integrated IP-based Design Framework for Distributed Embedded Systems	claim
29	147	Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching	claim
30	147	ENOR: Model Order Reduction of RLC Circuits Using Nodal Equations for Efficient Factorization	claim
31	146	Design Strategy of On-Chip Inductors for Highly Integrated RF Systems	claim
32	145	Dynamically Reconfigurable Architecture for Image Processor Applications	claim
33	143	MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells	claim
34	142	Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification	claim
35	141	Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems	claim
36	140	An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications	claim
37	139	Dynamic Power Management Based on Continuous-Time Markov Decision Processes	claim
38	139	Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing	claim
39	138	Robust Rational Function Approximation Algorithm for Model Generation	claim
40	138	Behavioral Synthesis Techniques for Intellectual Property Protection	claim
41	138	CAD Directions for High Performance Asynchronous Circuits	claim
42	137	Constraint Management for Collaborative Electronic Design	claim
43	137	A Practical Approach to Multiple-Class Retiming	claim
44	136	ICEBERG: An Embedded In-Circuit Emulator Synthesizer for Microcontrollers	claim
45	136	IC Analyses Including Extracted Inductance Models	claim
46	135	Panel: What is the Proper System on Chip Design Methodology	claim
47	134	Representation of Function Variants for Embedded System Optimization and Synthesis	claim
48	134	Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback	claim
49	133	On Thermal Effects in Deep Sub-Micron VLSI Interconnects	claim
50	133	The Simulation and Design of Integrated Inductors	claim
51	132	A Multiscale Method for Fast Capacitance Extraction	claim
52	132	Common-Case Computation: A High-Level Technique for Power and Performance Optimization	claim
53	131	Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology	claim
54	131	Verification of a Microprocessor Using Real World Applications	claim
55	131	Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization	claim
56	131	Design Considerations for Battery-Powered Electronics	claim
57	131	Embedded Application Design Using a Real-Time OS	claim
58	130	Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting	claim
59	130	Java Driven Codesign and Prototyping of Networked Embedded Systems	claim
60	130	A Model for Scheduling Protocol-Constrained Components and Environments	claim
61	130	Soft Scheduling in High Level Synthesis	claim
62	130	Application of High Level Interface-Based Design to Telecommunications System Hardware	claim
63	129	Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction	claim
64	129	Subwavelength Lithography and Its Potential Impact on Design and EDA	claim
65	129	Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design	claim
66	128	Symbolic Model Checking Using SAT Procedures instead of BDDs	claim
67	128	Using Lower Bounds During Dynamic BDD Minimization	claim
68	128	A Framework for Collaborative and Distributed Web-Based Design	claim
69	127	A CAD Tool for Optical MEMS	claim
70	127	Functional Timing Analysis for IP Characterization	claim
71	126	Module Placement for Analog Layout Using the Sequence-Pair Representation	claim
72	126	Optimization of Inductor Circuits via Geometric Programming	claim
73	126	Time-Mapped Harmonic Balance	claim
74	126	Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints	claim
75	125	Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks	claim
76	125	Model-Reduction of Nonlinear Circuits Using Krylov-Space Techniques	claim
77	125	ECL: A Specification Environment for System-Level Design	claim
78	125	Model Order-Reduction of RC(L) Interconnect Including Variational Analysis	claim
79	124	Effective Iterative Techniques for Fingerprinting Design IP	claim
80	124	Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions	claim
81	124	Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme	claim
82	124	Improved Approximate Reachability Using Auxiliary State Variables	claim
83	124	A Reordering Technique for Efficient Code Motion	claim
84	123	Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms	claim
85	123	Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings	claim
86	123	Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology	claim
87	122	Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits	claim
88	122	Robust Techniques for Watermarking Sequential Circuit Designs	claim
89	122	Functional Verification of the Equator MAP1000 Microprocessor	claim
90	122	Exact Memory Size Estimation for Array Computations without Loop Unrolling	claim
91	121	Efficient Capacitance Computation for Structures with Non-Uniform Adaptive Surface Meshes	claim
92	121	Engineering Change: Methodology and Applications to Behavioral and System Synthesis	claim
93	121	Synthesis of Embedded Software Using Free-Choice Petri Nets	claim
94	121	Vertical Benchmarks for CAD	claim
95	121	Panel: Cell Libraries - Build vs. Buy; Static vs. Dynamic	claim
96	121	Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression System	claim
97	121	Automated Phase Assignment for the Synthesis of Low Power Domino Circuits	claim
98	120	Verifying Large-Scale Multiprocessors Using an Abstract Verification Environment	claim
99	120	A Framework for User Assisted Design Space Exploration	claim
100	119	MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search	claim
101	119	Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications	claim
102	119	Microprocessor Based Testing for Core-Based System on Chip	claim
103	119	Crosstalk Minimization Using Wire Perturbations	claim
104	118	A Methodology for Accurate Performance Evaluation in Architecture Exploration	claim
105	118	A Two-State Methodology for RTL Logic Simulation	claim
106	118	SOI Digital CMOS VLSI - a Design Perspective	claim
107	118	Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style	claim
108	116	Customized Instruction-Sets for Embedded Processors	claim
109	116	Description and Simulation of Hardware/Software Systems with Java	claim
110	115	Parametric Representations of Boolean Constraints	claim
111	114	Hypergraph Partitioning with Fixed Vertices	claim
112	114	Parasitic Extraction Accuracy - How Much is Enough?	claim
113	114	An O-Tree Representation of Non-Slicing Floorplan and Its Applications	claim
114	114	The Jini Architecture: Dynamic Services in a Flexible Network	claim
115	113	Equivalent Elmore Delay for RLC Trees	claim
116	113	A Novel VLSI Layout Fabric for Deep Sub-Micron Applications	claim
117	113	Virtual Simulation of Distributed IP-based Designs	claim
118	113	IC Test Using the Energy Consumption Ratio	claim
119	112	Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software	claim
120	112	Enhancing Simulation with BDDs and ATPG	claim
121	112	Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations	claim
122	110	Improving Symbolic Traversals by Means of Activity Profiles	claim
123	109	Relaxation and Clustering in a Local Search Framework: Application to Linear Placement	claim
124	109	Multi-Time Simulation of Voltage-Controlled Oscillators	claim
125	108	Software Environment for a Multiprocessor DSP	claim
126	107	Maximizing Performance by Retiming and Clock Skew Scheduling	claim
127	107	Performance-Driven Integration of Retiming and Resynthesis	claim
128	107	A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware	claim
129	107	Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS	claim
130	106	Verification and Management of a Multimillion-Gate Embedded Core Design	claim
131	106	Why is ATPG Easy?	claim
132	106	Distributed Application Development with Inferno	claim
133	105	HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the Night	claim
134	104	FAR-DS: Full-Plane AWE Routing with Driver Sizing	claim
135	104	Optimization-Intensive Watermarking Techniques for Decision Problems	claim
136	103	Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems	claim
137	102	Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses	claim
138	101	Hardware Reuse at the Behavioral Level	claim
139	100	Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning	claim
140	94	Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems	claim
141	91	Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic	claim

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