4359 search results - page 20 / 872 » Automated Pipeline Design |
ASAP
2000
IEEE
13 years 11 months ago
2000
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
INFOCOM
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract—Many network processing applications require wirespeed access to large data structures or a large amount of flowlevel data, but the capacity of SRAMs is woefully inadeq...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
: This paper presents a self-calibration method for designing high speed pipeline ADCs. Unlike all existing calibration algorithms, the proposed calibration does not insert any tes...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...