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search results - page 238 / 872
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Automated Pipeline Design
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110
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1999
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Functional Timing Analysis for IP Characterization
16 years 5 months ago
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Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, ...
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Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations
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Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
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2000
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High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system
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V. E. Boros, Aleksandar D. Rakic, Sri Parameswaran
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Interconnect testing in cluster-based FPGA architectures
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testlab.ics.uci.edu
Ian G. Harris, Russell Tessier
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Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
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Chung-Yang Huang, Kwang-Ting Cheng
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