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ICCV
2011
IEEE
12 years 8 months ago
A robust pipeline for rapid feature-based pre-alignment of dense range scans
Aiming at reaching an interactive and simplified usage of high-resolution 3D acquisition systems, this paper presents a fast and automated technique for pre-alignment of dense ra...
Francesco Bonarrigo, Alberto Signoroni, Riccardo L...
ISCA
2003
IEEE
112views Hardware» more  ISCA 2003»
14 years 1 months ago
A Pipelined Memory Architecture for High Throughput Network Processors
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
Timothy Sherwood, George Varghese, Brad Calder
ARVLSI
1999
IEEE
112views VLSI» more  ARVLSI 1999»
14 years 9 days ago
Architectural Considerations for Application-Specific Counterflow Pipelines
Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for ...
Bruce R. Childers, Jack W. Davidson
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
14 years 28 days ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
MICRO
2010
IEEE
119views Hardware» more  MICRO 2010»
13 years 2 months ago
Task Superscalar: An Out-of-Order Task Pipeline
We present Task Superscalar, an abstraction of instruction-level out-of-order pipeline that operates at the tasklevel. Like ILP pipelines, which uncover parallelism in a sequential...
Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex...