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ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
13 years 11 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
BMCBI
2011
12 years 11 months ago
CLOTU: An online pipeline for processing and clustering of 454 amplicon reads into OTUs followed by taxonomic annotation
Background: The implementation of high throughput sequencing for exploring biodiversity poses high demands on bioinformatics applications for automated data processing. Here we in...
Surendra Kumar, Tor Carlsen, Bjørn-Helge Me...
BMCBI
2010
163views more  BMCBI 2010»
13 years 3 months ago
RISCI - Repeat Induced Sequence Changes Identifier: a comprehensive, comparative genomics-based, in silico subtractive hybridiza
Background -: The availability of multiple whole genome sequences has facilitated in silico identification of fixed and polymorphic transposable elements (TE). Whereas polymorphic...
Vipin Singh, Rakesh K. Mishra
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 3 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
MAM
2006
124views more  MAM 2006»
13 years 7 months ago
Design optimization and space minimization considering timing and code size via retiming and unfolding
The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such a...
Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, M...