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159
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RTSS
2006
IEEE
15 years 11 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
161
Voted
SC
1995
ACM
15 years 9 months ago
Input/Output Characteristics of Scalable Parallel Applications
Rapid increases in computing and communication performance are exacerbating the long-standing problem of performance-limited input/output. Indeed, for many otherwise scalable para...
Phyllis Crandall, Ruth A. Aydt, Andrew A. Chien, D...
147
Voted
EMSOFT
2007
Springer
15 years 11 months ago
WCET estimation for executables in the presence of data caches
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
Rathijit Sen, Y. N. Srikant
142
Voted
PLDI
2003
ACM
15 years 10 months ago
Predicting whole-program locality through reuse distance analysis
Profiling can accurately analyze program behavior for select data inputs. We show that profiling can also predict program locality for inputs other than profiled ones. Here loc...
Chen Ding, Yutao Zhong
186
Voted
TII
2010
124views Education» more  TII 2010»
15 years 2 days ago
Address-Independent Estimation of the Worst-case Memory Performance
Abstract--Real-time systems are subject to temporal constraints and require a schedulability analysis to ensure that task execution finishes within lower and upper specified bounds...
Basilio B. Fraguela, Diego Andrade, Ramon Doallo