53 search results - page 2 / 11 » Automatic Calibration of Performance Models on Heterogeneous... |
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
FPL
2009
Springer
14 years 7 days ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
EUROPAR
2008
Springer
13 years 9 months ago
2008
Springer
We describe a software solution to the problem of automatic parallelization of linear algebra code on multi-processor and multi-core architectures. This solution relies on the defi...
SAC
2009
ACM
14 years 2 months ago
2009
ACM
Parallel architectures are the way of the future, but are notoriously difficult to program. In addition to the low-level constructs they often present (e.g., locks, DMA, and non-...
SBACPAD
2008
IEEE
14 years 2 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...