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» Automatic Clock Abstraction from Sequential Circuits
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FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
14 years 4 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
PATMOS
2007
Springer
14 years 1 months ago
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...
Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jia...
BIRTHDAY
2003
Springer
14 years 27 days ago
Digital Algebra and Circuits
Abstract. Digital numbers D are the world’s most popular data representation: nearly all texts, sounds and images are coded somewhere in time and space by binary sequences. The m...
Jean Vuillemin
AAAI
2010
13 years 9 months ago
Representation Discovery in Sequential Decision Making
Automatically constructing novel representations of tasks from analysis of state spaces is a longstanding fundamental challenge in AI. I review recent progress on this problem for...
Sridhar Mahadevan
ASPDAC
2009
ACM
161views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Risk aversion min-period retiming under process variations
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
Jia Wang, Hai Zhou