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ASAP
2008
IEEE
105views Hardware» more  ASAP 2008»
13 years 9 months ago
Fast custom instruction identification by convex subgraph enumeration
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. &Ou...
CC
2005
Springer
195views System Software» more  CC 2005»
13 years 9 months ago
Compilation of Generic Regular Path Expressions Using C++ Class Templates
Various techniques for the navigation and matching of data structures using path expressions have been the subject of extensive investigations. No matter whether such techniques ar...
Luca Padovani
CODES
2008
IEEE
13 years 8 months ago
Software optimization for MPSoC: a mpeg-2 decoder case study
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...
Eric Cheung, Harry Hsieh, Felice Balarin
IPPS
2006
IEEE
14 years 29 days ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
DAC
2005
ACM
14 years 8 months ago
Automatic generation of customized discrete fourier transform IPs
This paper presents a parameterized soft core generator for the discrete Fourier transform (DFT). Reusable IPs of digital signal processing (DSP) kernels are important time-saving...
Grace Nordin, Peter A. Milder, James C. Hoe, Marku...