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CODES
2006
IEEE
15 years 10 months ago
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies
Real-time multi-media applications are increasingly being mapped onto MPSoC (multi-processor system-on-chip) platforms containing hardware-software IPs (intellectual property) alo...
Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nali...
MASCOTS
2003
15 years 5 months ago
Synthesizing Representative I/O Workloads Using Iterative Distillation
Storage systems designers are still searching for better methods of obtaining representative I/O workloads to drive studies of I/O systems. Traces of production workloads are very...
Zachary Kurmas, Kimberly Keeton, Kenneth Mackenzie
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
16 years 1 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
FPGA
2006
ACM
117views FPGA» more  FPGA 2006»
15 years 8 months ago
Context-free-grammar based token tagger in reconfigurable devices
In this paper, we present reconfigurable hardware architecture for detecting semantics of streaming data on 1+ Gbps networks. The design leverages on the characteristics of contex...
Young H. Cho, James Moscola, John W. Lockwood
ASPDAC
2007
ACM
90views Hardware» more  ASPDAC 2007»
15 years 8 months ago
Protocol Transducer Synthesis using Divide and Conquer approach
One of the efficient design methodologies for large scale System on a Chip (SoC) is IP-based design. In this methodology, a system is considered as a set of components and intercon...
Shigeru Watanabe, Kenshu Seto, Y. Ishikawa, Satosh...