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DATE
2007
IEEE
72views Hardware» more  DATE 2007»
14 years 3 months ago
The impact of loop unrolling on controller delay in high level synthesis
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan ...
GECCO
2007
Springer
167views Optimization» more  GECCO 2007»
14 years 3 months ago
Genetically designed heuristics for the bin packing problem
The bin packing problem (BPP) is a real-world problem that arises in different industrial applications related to minimization of space or time. The aim of this research is to au...
Oana Muntean
ICTAI
2006
IEEE
14 years 3 months ago
Hierarchical Language Models for Expert Finding in Enterprise Corpora
Enterprise corpora contain evidence of what employees work on and therefore can be used to automatically find experts on a given topic. We present a general approach for represen...
Desislava Petkova, W. Bruce Croft
AIME
2005
Springer
14 years 2 months ago
Ontology-Driven Extraction of Linguistic Patterns for Modelling Clinical Guidelines
Evidence-based clinical guidelines require frequent updates due to research and technology advances. The quality of guideline updates can be improved if the knowledge underlying th...
Radu Serban, Annette ten Teije, Frank van Harmelen...
FCCM
2003
IEEE
185views VLSI» more  FCCM 2003»
14 years 2 months ago
Implementation of a Content-Scanning Module for an Internet Firewall
A module has been implemented in Field Programmable Gate Array (FPGA) hardware that scans the content of Internet packets at Gigabit/second rates. All of the packet processing ope...
James Moscola, John W. Lockwood, Ronald Prescott L...