57 search results - page 5 / 12 » Automatic On-chip Memory Minimization for Data Reuse |
NPL
2006
13 years 7 months ago
2006
The authors previously proposed a self-organizing Hierarchical Cerebellar Model Articulation Controller (HCMAC) neural network containing a hierarchical GCMAC neural network and a ...
FCCM
2000
IEEE
13 years 11 months ago
2000
IEEE
Mapping computations written in high-level programming languages to FPGA-based computing engines requires programmers to generate the datapath responsible for the core of the comp...
ICPP
1998
IEEE
13 years 11 months ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we present a mechanism for automatic management of the memory hierarchy, including secondary storage, in the context of a global address space parallel programming ...
ASPLOS
1991
ACM
13 years 11 months ago
1991
ACM
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchies. Instead of operating on entire rows or columns of an array, blocked algorith...