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VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 7 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
FPL
2000
Springer
143views Hardware» more  FPL 2000»
13 years 11 months ago
Memory Access Schemes for Configurable Processors
Abstract. This work discusses the Memory Architecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface that supports both irregular (via configu...
Holger Lange, Andreas Koch
PPOPP
1997
ACM
13 years 11 months ago
Effective Fine-Grain Synchronization for Automatically Parallelized Programs Using Optimistic Synchronization Primitives
As shared-memory multiprocessors become the dominant commodity source of computation, parallelizing compilers must support mainstream computations that manipulate irregular, point...
Martin C. Rinard
ICCS
2004
Springer
14 years 26 days ago
Towards a Generalised Runtime Environment for Parallel Haskells
Abstract. Implementations of parallel dialects (or: coordination languages) on a functional base (or: computation) language always have to extend complex runtime environments by th...
Jost Berthold
ASPLOS
2010
ACM
14 years 2 months ago
Conservation cores: reducing the energy of mature computations
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip tha...
Ganesh Venkatesh, Jack Sampson, Nathan Goulding, S...