51 search results - page 1 / 11 » Automatic Verification of Sequential Circuit Designs |
CHDL
1993
13 years 8 months ago
1993
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DAC
1995
ACM
13 years 10 months ago
1995
ACM
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
CAV
1994
Springer
13 years 11 months ago
1994
Springer
This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on abehavioralseman...
FMCAD
2000
Springer
13 years 10 months ago
2000
Springer
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...