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» Automatic Verification of Timed Circuits
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DAC
2009
ACM
14 years 12 months ago
Computing bounds for fault tolerance using formal techniques
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
André Sülflow, Görschwin Fey, Rol...
FTCS
1998
114views more  FTCS 1998»
14 years 7 days ago
Verification of a Safety-Critical Railway Interlocking System with Real-Time Constraints
Ensuring the correctness of computer systems used in lifecritical applications is very difficult. The most commonly used verification methods, simulation and testing, are not exha...
Vicky Hartonas-Garmhausen, Sérgio Vale Agui...
FORMATS
2009
Springer
14 years 2 months ago
Stochastic Games for Verification of Probabilistic Timed Automata
Probabilistic timed automata (PTAs) are used for formal modelling and verification of systems with probabilistic, nondeterministic and real-time behaviour. For non-probabilistic ti...
Marta Z. Kwiatkowska, Gethin Norman, David Parker
TCAD
2008
98views more  TCAD 2008»
13 years 10 months ago
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
Khaled R. Heloue, Farid N. Najm
HASE
2008
IEEE
13 years 11 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri