Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models

Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timing verification, such as the use of process corners and predefined timing margins, cannot readily handle within-die variations. Recently, statistical static timing analysis (SSTA) has been proposed as a way to deal with variability. Although many powerful techniques have been proposed, the fact that SSTA requires a significant change of methodology has delayed its wide adoption. In this paper, we propose a framework whereby the familiar concepts of corners and margins, which are generally meaningful at the transistor or cell level, are elevated to the chip level in order to handle within-die variations. This is achieved by using high-level models, such as the generic path model or the generic circuit model with different classes of paths, to represent the behavior of typical designs. These models allow us to d...

• Type: Journal
• Year: 2008
• Where: TCAD
• Authors: Khaled R. Heloue, Farid N. Najm
• Keywords: Excessive Timing Yield, Process Variations, Statistical Static Timing Analysis, TCAD 2008