302 search results - page 18 / 61 » Automatic Verification of Timed Circuits |
DAC
2005
ACM
14 years 12 months ago
2005
ACM
We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending con...
DAC
2003
ACM
14 years 4 months ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
ENTCS
2006
13 years 11 months ago
2006
Patterns for property specification enable non-experts to write formal specifications that can be used for automatic model checking. The existing patterns identified in [6] allow ...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward w...
INTERSPEECH
2010
13 years 5 months ago
2010
Being able to recognize people from their voice is a natural ability that we take for granted. Recent advances have shown significant improvement in automatic speaker recognition ...