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ERSA
2004
134views Hardware» more  ERSA 2004»
13 years 9 months ago
A High Performance Application Representation for Reconfigurable Systems
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
Wenrui Gong, Gang Wang, Ryan Kastner
IPPS
2010
IEEE
13 years 5 months ago
Inter-block GPU communication via fast barrier synchronization
The graphics processing unit (GPU) has evolved from a fixedfunction processor with programmable stages to a programmable processor with many fixed-function components that deliver...
Shucai Xiao, Wu-chun Feng
ICDCS
2012
IEEE
11 years 10 months ago
PREPARE: Predictive Performance Anomaly Prevention for Virtualized Cloud Systems
Abstract—Virtualized cloud systems are prone to performance anomalies due to various reasons such as resource contentions, software bugs, and hardware failures. In this paper, we...
Yongmin Tan, Hiep Nguyen, Zhiming Shen, Xiaohui Gu...
SPAA
2006
ACM
14 years 1 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
14 years 2 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...