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ATS
1998
IEEE
170views Hardware» more  ATS 1998»
13 years 11 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
CVPR
2007
IEEE
14 years 9 months ago
Groupwise Shape Registration on Raw Edge Sequence via A Spatio-Temporal Generative Model
Groupwise shape registration of raw edge sequence is addressed. Automatically extracted edge maps are treated as noised input shape of the deformable object and their registration...
Huijun Di, Rao Naveed Iqbal, Guangyou Xu, Linmi Ta...
TC
1998
13 years 7 months ago
Abstraction Techniques for Validation Coverage Analysis and Test Generation
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Ho...
BMCBI
2006
159views more  BMCBI 2006»
13 years 7 months ago
EVEREST: automatic identification and classification of protein domains in all protein sequences
Background: Proteins are comprised of one or several building blocks, known as domains. Such domains can be classified into families according to their evolutionary origin. Wherea...
Elon Portugaly, Amir Harel, Nathan Linial, Michal ...
KBSE
2007
IEEE
14 years 1 months ago
Testing concurrent programs using value schedules
Concurrent programs are difficult to debug and verify because of the nondeterministic nature of concurrent executions. A particular concurrency-related bug may only show up under ...
Jun Chen, Steve MacDonald