190 search results - page 31 / 38 » Automatically Mapping Code on an Intelligent Memory Architec... |
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
Extracting performance from many-core architectures requires software engineers to create multi-threaded applications, which significantly complicates the already daunting task of...
SEUS
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Writing shared-memory parallel programs is error-prone. Among the concurrency errors that programmers often face are atomicity violations, which are especially challenging. They h...
GECCO
2005
Springer
14 years 28 days ago
2005
Springer
Existing Recurrent Neural Networks (RNNs) are limited in their ability to model dynamical systems with nonlinearities and hidden internal states. Here we use our general framework...