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ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
14 years 2 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
AEI
2010
126views more  AEI 2010»
13 years 7 months ago
Engineering intelligent information-processing systems with CAST
The CoSy Architecture Schema Toolkit (CAST) is a new software toolkit, and related processing paradigm, which supports the construction and exploration of information-processing a...
Nick Hawes, Jeremy Wyatt
CASES
2006
ACM
14 years 1 months ago
A dynamic code placement technique for scratchpad memory using postpass optimization
In this paper, we propose a fully automatic dynamic scratchpad memory (SPM) management technique for instructions. Our technique loads required code segments into the SPM on deman...
Bernhard Egger, Chihun Kim, Choonki Jang, Yoonsung...
ISPAN
1997
IEEE
13 years 11 months ago
CASS: an efficient task management system for distributed memory architectures
The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the applica...
Jing-Chiou Liou, Michael A. Palis
ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
14 years 1 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...