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DAC
2008
ACM
14 years 8 months ago
Automated transistor sizing for FPGA architecture exploration
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
Ian Kuon, Jonathan Rose
DAC
2008
ACM
14 years 8 months ago
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts
End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In t...
Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. R...
AND
2009
13 years 5 months ago
Tools for monitoring, visualizing, and refining collections of noisy documents
Developing better systems for document image analysis requires understanding errors, their sources, and their effects. The interactions between various processing steps are comple...
Daniel P. Lopresti, George Nagy
CAISE
2010
Springer
13 years 8 months ago
Design and Verification of Instantiable Compliance Rule Graphs in Process-Aware Information Systems
For enterprises it has become crucial to check compliance of their business processes with certain rules such as medical guidelines or financial regulations. When automating compli...
Linh Thao Ly, Stefanie Rinderle-Ma, Peter Dadam
FORTE
2001
13 years 9 months ago
Stepwise Design with Message Sequence Charts
Use cases are useful in various stages of the software process. They are very often described using text that has to be interpreted by system designers. This could lead to implemen...
Ferhat Khendek, Stephan Bourduas, Daniel Vincent