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» Automating software feature verification
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ENTCS
2008
106views more  ENTCS 2008»
13 years 8 months ago
Towards Verifying Model Transformations
In model-based software development, a complete design and analysis process involves designing the system using the design language, converting it into the analysis language, and ...
Anantha Narayanan, Gabor Karsai
FMCAD
2000
Springer
14 years 3 days ago
Model Checking Synchronous Timing Diagrams
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Ke...
DAC
2000
ACM
14 years 9 months ago
Formal verification of iterative algorithms in microprocessors
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
Mark Aagaard, Robert B. Jones, Roope Kaivola, Kath...
DATE
2004
IEEE
184views Hardware» more  DATE 2004»
14 years 7 days ago
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
Panagiotis Manolios, Sudarshan K. Srinivasan
GPCE
2009
Springer
14 years 1 months ago
Safe composition of non-monotonic features
Programs can be composed from features. We want to verify automatically that all legal combinations of features can be composed safely without errors. Prior work on this problem a...
Martin Kuhlemann, Don S. Batory, Christian Kä...