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» Automating software feature verification
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DAC
2003
ACM
14 years 9 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
FAC
2007
170views more  FAC 2007»
13 years 8 months ago
Are the Logical Foundations of Verifying Compiler Prototypes Matching user Expectations?
Abstract. The Verifying Compiler (VC) project proposals suggest that mainstream software developers are its targeted end-users. Like other software engineering efforts, the VC proj...
Patrice Chalin
ICSE
2004
IEEE-ACM
14 years 1 months ago
Precise Modeling of Design Patterns in UML
Prior research attempts to formalize the structure of object-oriented design patterns for a more precise specification of design patterns. It also allows automation support to be ...
Jeffrey Ka-Hing Mak, Clifford Sze-Tsan Choy, Danie...
SIGSOFT
2005
ACM
14 years 9 months ago
Fluent temporal logic for discrete-time event-based models
Fluent model checking is an automated technique for verifying that an event-based operational model satisfies some state-based declarative properties. The link between the event-b...
Emmanuel Letier, Jeff Kramer, Jeff Magee, Sebasti&...
SIMUTOOLS
2008
13 years 10 months ago
Transforming sources to petri nets: a way to analyze execution of parallel programs
Model checking is a suitable formal technique to analyze parallel programs' execution in an industrial context because automated tools can be designed and operated with very ...
Jean-Baptiste Voron, Fabrice Kordon