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» Automating software feature verification
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ITNG
2010
IEEE
14 years 1 months ago
BAUT: A Bayesian Driven Tutoring System
—This paper presents the design of BAUT, a tutoring system that explores statistical approach for providing instant project failure analysis. Driven by a Bayesian Network (BN) in...
Song Tan, Kai Qian, Xiang Fu, Prabir Bhattacharya
HASE
2007
IEEE
14 years 10 days ago
Multiple Pre/Post Specifications for Heap-Manipulating Methods
Automated verification plays an important role for high assurance software. This typically uses a pair of pre/post conditions as a formal (but possibly partial) specification of e...
Wei-Ngan Chin, Cristina David, Huu Hai Nguyen, She...
EICS
2009
ACM
14 years 3 months ago
Engineering crowd interaction within smart environments
Smart environments (e.g., airports, hospitals, stadiums, and other physical spaces using ubiquitous computing to empower many mobile people) provide novel challenges for usability...
Michael D. Harrison, Mieke Massink, Diego Latella
CODES
2004
IEEE
14 years 6 days ago
RTOS-centric hardware/software cosimulator for embedded system design
This paper presents an RTOS-centric hardwareisoftware cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is tha...
Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiy...
SIGCOMM
2010
ACM
13 years 8 months ago
capDL: a language for describing capability-based systems
Capabilities provide an access control model that can be used to construct systems where safety of protection can be precisely determined. However, in order to be certain of the s...
Ihor Kuz, Gerwin Klein, Corey Lewis, Adam Walker