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SC
1992
ACM
13 years 11 months ago
Compiler Code Transformations for Superscalar-Based High Performance Systems
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
Scott A. Mahlke, William Y. Chen, John C. Gyllenha...
PARLE
1992
13 years 11 months ago
Characterizing the Paralation Model using Dynamic Assignment
Collection-oriented languages provide high-level constructs for describing computations over collections. These languages are becoming increasingly popular with the advent of massi...
Eric T. Freeman, Daniel P. Friedman
CGO
2006
IEEE
14 years 26 days ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
ICCD
2004
IEEE
125views Hardware» more  ICCD 2004»
14 years 3 months ago
IPC Driven Dynamic Associative Cache Architecture for Low Energy
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
Sriram Nadathur, Akhilesh Tyagi
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 2 days ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...