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ICS
1999
Tsinghua U.
14 years 2 months ago
Reorganizing global schedules for register allocation
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
Gang Chen, Michael D. Smith
SC
1992
ACM
14 years 2 months ago
Compiler Code Transformations for Superscalar-Based High Performance Systems
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
Scott A. Mahlke, William Y. Chen, John C. Gyllenha...
LREC
2010
169views Education» more  LREC 2010»
13 years 11 months ago
Using Comparable Corpora to Adapt a Translation Model to Domains
Statistical machine translation (SMT) requires a large parallel corpus, which is available only for restricted language pairs and domains. To expand the language pairs and domains...
Hiroyuki Kaji, Takashi Tsunakawa, Daisuke Okada
ESCIENCE
2006
IEEE
14 years 4 months ago
A Unified Data Grid Replication Framework
Modern scientific experiments can generate large amounts of data, which may be replicated and distributed across multiple resources to improve application performance and fault to...
Tim Ho, David Abramson
EUROPAR
2001
Springer
14 years 2 months ago
Using a Swap Instruction to Coalesce Loads and Stores
A swap instruction, which exchanges a value in memory with a value of a register, is available on many architectures. The primary application of a swap instruction has been for pro...
Apan Qasem, David B. Whalley, Xin Yuan, Robert van...